Analog-devices ADSP-2181 Manual de usuario descargar pdf (Pagina 22)

ADSP-2181/ADSP-2183

REV. 0

–22–

ADSP-2181/ADSP-2183

Parameter Min Max Unit

Bus Request/Grant

Timing Requirements:

BR Hold after CLKOUT High

0.25t

+ 2 ns

BR Setup before CLKOUT Low

0.25t

+ 17 ns

Switching Characteristics:

CLKOUT High to xMS, 0.25t

+ 10 ns

RD, WR Disable

SDB

xMS, RD, WR

Disable to

BG Low 0 ns

BG High to xMS,

RD, WR Enable 0 ns

SEC

xMS, RD, WR

Enable to CLKOUT High 0.25t

– 7 ns

SDBH

xMS, RD, WR

Disable to

BGH Low

0ns

SEH

BGH High to xMS,

RD, WR Enable

0ns

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS

BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on

the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

CLKOUT

SDB

SEC

SDBH

SEH

CLKOUT

PMS, DMS

BMS, RD

BGH

Figure 24. Bus Request–Bus Grant

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 39 40

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