Analog Devices AD9843A Manual de usuario descargar pdf (Pagina 9)

AD9843A

–9–

REV. 0

CCD-MODE AND AUX-MODE TIMING

N–10 N–9N–8N–1N

N N+1 N+2 N+9 N+10

INH

NOTES:

1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.

2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.

SHP

SHD

DATACLK

OUTPUT

DATA

CCD

SIGNAL

Figure 5. CCD-Mode Timing

CCD

SIGNAL

EFFECTIVE PIXELS

CLPOB

CLPDM

OPTICAL BLACK PIXELS

HORIZONTAL

BLANKING

DUMMY PIXELS EFFECTIVE PIXELS

PBLK

NOTES:

1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.

2. PBLK SIGNAL IS OPTIONAL.

3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.

OUTPUT

DATA

EFFECTIVE PIXEL DATA

OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA

Figure 6. Typical CCD-Mode Line Clamp Timing

DATACLK

OUTPUT

DATA

VIDEO

SIGNAL

N+1

N+2

N+8

N+9

N–10 N–9N–8N–1N

Figure 7. AUX-Mode Timing

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Complete 10-Bit 20 MSPS 1
CCD Signal Processor 1
AD9843A–SPECIFICATIONS 2
CCD-MODE SPECIFICATIONS 3
TIMING SPECIFICATIONS 5
DEFINITIONS OF SPECIFICATIONS 7
TPC 1. Power vs. Sample Rate 8
Figure 5. CCD-Mode Timing 9
Figure 7. AUX-Mode Timing 9
Register Address Data Bits 10
*Must be set to zero 11
Figure 12. CDS Gain Curve 12
AUX2-Mode 13
Variable Gain Amplifier 13
Optical Black Clamp 13
A/D Converter 13
AUX1-Mode 13
APPLICATIONS INFORMATION 15
OUTLINE DIMENSIONS 16
48-Lead LQFP 16

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Analog Devices AD9843A Manual de usuario Pagina 9

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